PM803F 3BDH000530R1 writes are not immediately mirrored to main memory

PM803F 3BDH000530R1 If data is written to the cache, at some point it must also be written to main memory; The timing of this write is called the write policy. In a write – to cache, each write to the cache results in a write to main memory. Alternatively, in a roll-back or write-back cache, writes are not immediately mirrored to main memory, but instead the cache tracks which locations have been overwritten and marks them as dirty. Only when data at these locations is ejected from the cache is it written back to main storage.

For this reason, read misses in a write-back cache may sometimes require two memory accesses to service: one to first write the dirty location to main storage, and another to read the new location from storage. In addition, writes to primary storage locations that have not been mapped in the write-back cache can drive out locations that are already dirty, thus freeing cache space for new storage locations.

The PM803F 3BDH000530R1 also has an intermediate policy. The cache can be write-straight, but writes can be held temporarily in a storage data queue, often allowing multiple stores to be processed together (which can reduce bus turnover and improve bus utilization).

The cache data from the PM803F 3BDH000530R1 May be used by other entities (for example, by direct memory access (DMA) or multi-core processors). In this case, the copy of the [①③ ③ ③ ③ ③ ⑦] ⑼ in the cache may expire or become invalid. Or, the CPU multiprocessor system updates the data in the cache and the copy of the data in the cache associated with the other CPU becomes stale. The communication protocol between cache managers that keep data consistent is called the cache consistency protocol.