FBM237 RH914XS maps table memory to be the same as the main memory

An early virtual memory system, IBM M44/44X, required access to the mapped table core memory stored in it before each programmatic access to the main memory. [23] Since there is no cache and the mapped table memory runs at the same speed as the main memory, this effectively halves the speed of memory access. Two early machines used page tables in main memory for mapping the IBM System/360 Model 67 and GE 645, both of which had a small associated memory as a cache for accessing the in-memory page tables. Before the first machine, both machines had main memory caches IBM System/360 Model 85 so the first hardware cache used in a computer system was not a data or instruction cache, but a TLB.

There are four types of caches, depending on whether the index or label corresponds to a physical or virtual address:

Physical index, physical tag (PIPT) Cache uses the physical address of the index and tag. While this is simple and avoids aliasing problems, it is also slow because the physical address must be looked up before it can be looked up in the cache (which may involve TLB misses and access to main storage).

Virtual index, virtual tag (VIVT) cache uses virtual addresses for indexes and tags. This caching scheme can lead to faster lookups because there is no need to consult the MMU first to determine the physical address of a given virtual address. However, VIVT has an alias problem where several different virtual addresses may point to the same physical address. As a result, these addresses will be cached separately, although the same storage is involved, leading to consistency problems. Although there are solutions to this problem [26] they do not apply to standard coherence protocols.