FLN3524A CPU3640 The cache mapped to the cache group

Compared to a directly mapped cache, a group association cache has a reduced number of bits for the cache group index it maps to a cache group, where multiple or blocks reside, such as a 2-way group association cache with 2 blocks and a 4-way group association cache with 4 blocks. Unused cache index bits become part of the tag bits compared to directly mapped caches. For example, a 2-way group association cache contributes 1 bit to the tag, while a 4-way group association cache contributes 2 bits to the tag.

The basic idea of multi-column caching [16] uses group indexes to map to cache groups, as traditional group association caches do, and adds tag bits to index paths in the group. For example, in the 4-way group association cache, these two bits are used to index route 00, route 01, route 10, and route 11. This dual cache index is called a “primary location map” and has the same latency as direct mapped access.

Numerous experiments [16] in multi-column cache designs show a hit rate of up to 90% for primary locations. If the cache map conflicts with a cache block in the primary location, the existing cache block will be moved to another cache path in the same group, which is called the “selected location.” Because the cache block of the new index is the most recently used (MRU) block, it is placed in the primary location in the multi-column cache in consideration of time locality.

Because multi-column caches are designed for highly correlated caches, the number of paths in each group is large; Therefore, it is easy to find the selected location in the collection. (3) ③ ③ ⑥ (5) ⑼ maintain the selected location index by the additional hardware for the main positions in the cache block.

Multi-column caches maintain a high hit ratio due to their high correlation, and have low latency comparable to direct-mapped caches due to their high hit ratio at primary locations. The concept of primary and selected locations in multi-column caches has been used in multiple cache designs for ARM Cortex R chips, Intel’s approach to predictive caching,IBM’s reconfigurable multiplexed associative cache, and Oracle’s alternative approach to dynamic caching based on address tag bits.