MVI56-MDA4 PROSOFT comes with 128 byte cache block

The Pentium 4 processor has an 8-way group associated with L1 data cache with a KiB size of 64 byte cache blocks. Therefore, there are 8 KiB / 64 = 128 cache blocks. The number of sets is equal to the number of cache blocks divided by the number of associated paths, giving 128/4 = 32 sets, so 25= 32 different exponents. There are two possible offsets of 6= 64. Since the CPU address is 32 bits wide, this means that the tag field is 32-5-6 = 21 bits.

The original Pentium 4 processor also had an 8-way group associated L2 integrated cache with a size of 256 KiB, with a cache block of 128 bytes. This means that the label field has 32-8-7 = 17 bits. [20]

Instruction cache requires only one flag bit per cache line entry: a significant bit. The significant bit indicates whether the cache block has loaded valid data.

On power-up, the hardware sets all significant bits in all caches to “invalid”. Some systems also set the significant bit to “invalid” at other times, such as when the multi-host bus snooping on the hardware in one processor’s cache hears an address broadcast from some other processor, and realizes that some block of data in the local cache is now old and should be marked as invalid.

Data caches typically require two flag bits per cache row, one significant bit and one dirty bit. Setting the dirty bit indicates that the associated cache row has been changed (” dirty “) since it was read from main storage, meaning that the processor has written data to the row and that the new value has not been propagated all the way to main storage.